In the working directory for the ISE project, find the Adder. Scroll to the first transition of signal a and look at signal s: instead of changing at the same time as signal a, like it did in the functional simulation, the signal transitions after a delay. You will need the VHDL wrapper and all netlists as well as their simulation models.
The cursor can be renamed by right-clicking on the white box in the lower-left. Simulation errors displayed in the ModelSim console. There should be a line saying Minimum period: 1.
For this design you will need the following files: AdderWrapper. You can create a new cursor by right-clicking at the bottom of the waveform and choosing New Cursor, or by using the Insert Cursor button on the toolbar.
Double-click on Simulate Behavioral Model and ModelSim will open, compile your full adder module and run the simulation code. To see an example of this, go back to your test fixture and change every instance of " 25" to " 1"; this means that the signals will change every two nanoseconds with check tasks in between , as opposed to every fifty nanoseconds.
If your simulation has any errors, the time of the error, the current output and the expected output will be displayed in blue in the ModelSim console the "Transcript" window. Waveforms will now appear for t1, t2 and t3. Zoom in closely on an OUT transition, and you should notice that on every other cycle, OUT changes to one value, then quickly changes to another value the expected value.
If your simulation has any errors, the time of the error, the current output and the expected output will be displayed in blue in the ModelSim console the "Transcript" window. Configure the page as shown below. This is not a problem for our current design, because everything changes before the next positive CLK edge.
Simulation errors displayed in the ModelSim console. A waveform with three cursors. In your test fixture, instead of manually changing the clock, some behavioral Verilog code can change it for you.
You will also notice that the output signals are red and have a value of "x" at the beginning of the simulation. A timing simulation with transitions every 2 ns. If it does not, it will print an error to the simulation console. A waveform with three cursors. ISE creates a skeleton test fixture for you. Click Next until you reach the Project Summary page and then click Finish.
A timing simulation of the clocked counter module.
Since the full adder only has three one-bit inputs, there are only eight possible input combinations, and your test fixture should simulate them all. This is why it is important to use timing simulation in addition to functional simulation. Simulation errors displayed in the ModelSim console. The outputs from the module are wires. Click OK to add the Verilog module to the project.